-- 32 XOR Gates
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
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entity XOR_Gate_32Bits is

	port(
		A 	: 	in 	std_logic_vector(31 downto 0);
		B 	: 	in 	std_logic_vector(31 downto 0);
		S 	: 	out 	std_logic_vector(31 downto 0)
	);
	
end XOR_Gate_32Bits;

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architecture Structural of XOR_Gate_32Bits is

	
	component XOR_Block is
		generic(WORD_SIZE : positive);
		port(
			A	:	in 	std_logic_vector(WORD_SIZE-1 downto 0);
			B 	: 	in 	std_logic_vector(WORD_SIZE-1 downto 0);
			S	:	out 	std_logic_vector(WORD_SIZE-1 downto 0)
			);
	end component;

begin

		xor_gate : XOR_Block
			generic map(32)
			port map(
				A => A,
				B => B,
				S => S
			);

end Structural;

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